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1 ixd611 ? 2007 ixys corporation all rights reserved features ? floating high side driver with boot-strap power supply along with a low side driver. ? fully operational to 600v ? 50v/ns dv/dt immunity ? gate drive power supply range: 10 - 35v ? undervoltage lockout for both output drivers ? outputs are in phase with inputs ? built using the advantages and compatibility of cmos and ixys hdmos tm processes ? latch-up protected over entire operating range ? high peak output current: 600 ma ? matched propagation delay for both outputs ? low output impedance ? low power supply current ? immune to negative voltage transients first release general description the ixd611, with its two inputs referenced to ground, has high speed low side and high side gate ouptuts to drive either a pair of n-channel mosfets or igbts in a half-bridge totem pole configuration. the high side driver can control a mosfet or igbt connected to a positive high voltage up to 600v. the logic input stages are compatible with ttl or cmos, have built-in hysteresis and are fully immune to latch up over the entire operating range. the ixd611 can withstand dv/dt on the output side up to 50v/ns. the ixd611 comes in either the 8-pin pdip (ixd611p1), 8-pin soic (IXD611S1), 14-pin pdip (ixd611p7), or the 14-pin soic (ixd611s7) packages. applications ? driving mosfets and igbts in half-bridge circuits ? high voltage, high side and low side drivers ? motor controls ? switch mode power supplies (smps) ? dc to dc converters ? class d switching amplifiers warning: the ixd611 is esd sensitive. ds99198a(10/07) up to 600v to load vcc hin lin gnd vcl hin lin dg vch hgo hs ls lgo figure 1a. typical circuit for ixd611p7/s7 figure 1b. typical circuit for ixd611p1/s1 600v, 600 ma high & low-side driver for n-channel mosfets and igbts up to 600v to load lgo hgo hs vch vcl hin lin ls vcc gnd lin hin ixd611 ixd611p1 8-pin dip ixd611p7 14-pin dip IXD611S1 8-pin soic ixd611s7 14-pin soic ordering information part number package type
2 ixd611 ixys reserves the right to change limits, test conditions, and dimensions. figure 2. ixd611 functional block diagram pin description and configuration symbol function description vcl supply voltage low side power supply. hin hs input high side input signal, ttl or cmos compatible; hgo in phase lin ls input low side input signal, ttl or cmos compatible; lgo in phase dg ground logic reference ground (not available for ixd611p1, IXD611S1) vch supply voltage high side floating power supply, referenced to hs hgo output high side driver output hs return high side floating ground lgo output low side driver output ls ground low side ground
3 ixd611 ? 2007 ixys corporation all rights reserved 7 6 5 figure 3a. pin configuration for ixd611p1 (8 pin dip) and IXD611S1 (8 pin soic) figure 3b. pin configuration for ixd611p7 (14 pin dip) and ixd611s7 (14 pin soic) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 hin lgo ls lin vcl vch hgo hs vcl hin lin ls lgo hs vch hgo 8 pin dip 8 pin soic 1 2 3 4 5 6 7 8 1 2 3 4 8 IXD611S1 ixd611p1 lin hgo nc nc nc nc dg ls lgo hs vch vcl nc hs nc nc nc vcl vch dg lin hgo lgo nc nc ls hin hin 8 14 13 12 11 10 9 1 2 3 4 5 6 7 14 pin dip 14 pin soic ixd611p7 ixd611s7
4 ixd611 ixys reserves the right to change limits, test conditions, and dimensions. symbol definition min max units v hs high side floating supply offset voltage -200 650 v v ch high side floating absolute voltage -0.3 35 v v hgo high side floating output voltage v hs - 0.3 v ch + 0.3 v v cl low side fixed supply voltage -0.3 35 v v lgo low side output voltage -0.3 v cl + 0.3 v v dg logic supply offset voltage (p7, s7 only) v ls - 0.7 v ls + 0.7 v v in logic input voltage(hin & lin) ls - 0.3 v cl + 0.3 v dv hs /dt allowable offset supply voltage transient 50 v/ns p d package power dissipation@ t a 25c 8 pin pdip 1.0 w 8 pin soic 0.625 w 14 pin pdip 1.6 w 14 pin soic 1.0 w r thja thermal resistance, junction-to-ambient 8 pin pdip 125 o c/w 8 pin soic 200 o c/w 14 pin pdip 75 o c/w 14 pin soic 120 o c/w t j junction temperature 150 o c t s storage temperature -55 150 o c t l lead temperature (soldering, 10 s) 300 o c absolute maximum ratings recommended operating conditions symbol definition min max units v hs high side floating supply offset voltage -200 600 v v ch high side floating supply absolute voltage 10 30 v v hgo high side floating output voltage v hs v ch v v cl low side fixed supply voltage 10 30 v v lgo low side output voltage 0 v cl v v dg logic supply offset voltage (p7, s7 only) v ls - 0.3 v ls + 0.3 v v in logic input voltage(hin, lin) v dg or ls v cl v t a ambient temperature -40 125 o c
5 ixd611 ? 2007 ixys corporation all rights reserved precaution : when performing the high voltage tests, adequate safety precautions should be taken. symbol definition test conditions min typ max units v inh logic ?1? input voltage v cl = v ch = 15v 2.7 v v inl logic ?0? input voltage v cl = v ch = 15v 2.4 v v hlgo / / v hhgo high level output voltage, i o = 20ma 0.22 0.3 v v ch -v hgo or v cl -v lgo v llgo / / v lhgo low level output voltage, i o = 20ma 0.16 0.25 v v hgo or v lgo i hl hs to ls bias current. v hs = 600v 0.12 0.2 ma i qhs quiescent v ch supply current v ch = 15v v in = 0v or v in = 5 v 0.7 0.8 ma i qls quiescent v cl supply current v cl = 15v v in = 0v or v in = 5 v 0.18 0.3 ma i in + logic ?1? input bias current v in = v supply = 15v 11 20 ua i in - logic ?0? input bias current v in = 0v 1 2 ua v chuv +v ch supply undervoltage positive going threshold. 7.5 8 8.5 v v chuv -v ch supply undervoltage negative going threshold. 7 7.3 8 v v cluv +v cl supply undervoltage positive going threshold 7.5 8 8.5 v v cluv -v cl supply undervoltage negative going threshold. 7 7.5 8 v v chuvh , v cluvh undervoltage hysteresis 0.3 0.6 v i go + hs or ls output high short circuit current; v go = 15v, v in = 5v, pw<10us 0.5 0.6 a i go - hs or ls output low short circuit current; v go = 15v, v in = 0v, pw<10us -0.6 -0.5 a dynamic electrical characteristics symbol definition test conditions min typ max units t on turn-on propagation delay v cl = v ch = 15v, c load = 1nf 180 200 ns t off turn-off propagation delay v cl = v ch = 15v, c load = 1nf 170 190 ns t r turn-on rise time v cl = v ch = 15v, c load = 1nf 28 35 ns t f turn-off fall time v cl = v ch = 15v, c load = 1nf 18 25 ns t dm delay matching, hs & ls turn-on/off c load = 1nf 10 20 ns static electrical characteristics
6 ixd611 ixys reserves the right to change limits, test conditions, and dimensions. timing waveform definitions figure 6. definitions of delay matching waveforms figure 5. definitions of switching time waveforms 50% 50% 10% 90% outgoing signal hin lin hgo lgo lgo hgo tdm tdm 50 % 50% hin lin 10% 10% hgo lgo 90% 90% tdon tdoff tr tf figure 4. input/ouput timing diagram ~ ~ ~ ~ ~ ~ 300khz 1mhz 600v 400v 0 f pwm v + + b u s s ( v ) h s s a m p l e t e s t e d f o r o p e r a t i o n 500v 100khz figure 7. device operating range: buss voltage vs. frequency tested in typical circuit configuration (refer to figure 9 & 10)
7 ixd611 ? 2007 ixys corporation all rights reserved figure 8. test circuit for allowable offset supply voltage transient. i x d 6 1 1 s 1 v ch hgo hs v cl lgo hin lin ls 1k 1k hin lin 1 2 3 4 vin+ vout- vout+ gnd vout- vout+ n d y 1 2 1 5 c 1 0 u f / 3 5 v 1uf/35v mlcc 1k v cl 1uf/35v mlcc 10uf/35v 15 5.1 1n5817 1n5817 5.1 15 18uh 0.47uf 0.47uf 2 0 / 5 w 2 0 / 5 w 0.1uf/1kv up to 500v v cl 1 10 11 12 15 14 5 6 7 8 ixcp 10m90s 1 2 3 30 ixth14n60p ixth14n60p figure 9. test circuit for high frequency, 750khz, operation. v ch , v cl = 15v hs lgo vch vcl hin lin ls hgo n/c 50 gnd dv/dt slope adjustment dc_dc boost ndy1215c vout+ vout- tx 30:1 1nf 10v 10v 10uf low esr 15v 10uf 0.1uf ixdn414 drive input up to 600v hgo out 1.5k 2w 20uf 1kv 10x0.1uf 1kv 100uf 25v low esr 100 ohm multi turn ixd611 measure dv/dt
8 ixd611 ixys reserves the right to change limits, test conditions, and dimensions. i x d 6 1 1 s 1 v ch hgo hs v cl lgo hin lin ls 1k 1k hin lin 1 2 3 4 vin+ vout- vout+ gnd vout- vout+ n d y 1 2 1 5 c 1 0 u f / 3 5 v 1uf/35v mlcc 1k v cl 1uf/35v mlcc 10uf/35v 51 5.1 1n5817 1n5817 5.1 51 0.1uf/1kv up to 600v v cl 1 10 11 12 15 14 5 6 7 8 ixcp 10m90s 1 2 3 30 ixth14n60p ixth14n60p figure 10. test circuit for low frequency, 75khz, operation. v ch , v cl = 15v
9 ixd611 ? 2007 ixys corporation all rights reserved rise times vs. supply voltage 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 supply voltage (v) rise time (ns) 1000 pf 100 pf fall times vs. supply voltage 0 5 10 15 20 25 0 5 10 15 20 25 30 35 40 supply voltage (v) fall time (ns) 1000 pf 100 pf rise / fall times vs. temperature v in = v supply = 15v c load = 1000pf 0 5 10 15 20 25 30 35 40 -50 0 50 100 150 temperature (c) rise / fall times (ns) fall rise propagation delay vs. temperature v in = v supply = 15v c load = 1000pf 150 155 160 165 170 175 180 185 190 -100 -50 0 50 100 150 temperature (c) propagation delay(ns) pos. going input neg. going input propagation delay vs. supply voltage c l = 1000pf v in = v supply 100 120 140 160 180 200 220 240 260 0 5 10 15 20 25 30 35 40 supply voltage (v) propagation delay (ns) high side positive going high side negative going l o w s i de pos itiv e go in g low side negative going under voltage lock out vs. temperature 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 -100 -50 0 50 100 150 temperature (c) lock out threshold (v) neg. going supply voltage pos. going supply voltage fig.12 fig. 14 fig. 16 fig. 11 fig. 13 fig.15
10 ixd611 ixys reserves the right to change limits, test conditions, and dimensions. quiescent supply current vs. supply voltage v in = "0" 0 0.2 0.4 0.6 0.8 1 1.2 0 5 10 15 20 25 30 35 40 supply voltage (v) quiescent current (ma) low side high side input threshold level vs. temperature v supply = 15v 0 0.5 1 1.5 2 2.5 3 3.5 4 -50 0 50 100 150 temperature (c) threshold level (v) neg. going input pos. going input quiescent current vs. temperature v in = "0" v supply = 15v both drivers combined 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.57 -50 0 50 100 150 temperature (c) quiescent current (ma) lin / hin bias current vs. temperature v supply = 15v 0 2 4 6 8 10 12 14 16 -50 0 50 100 150 temperature (c) input bias current (ua) v in = 5v v in = 15v input threshold level vs. supply voltage 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 5 10 15 20 25 30 35 40 supply voltage (v) threshold level (v) positve going negative going lin / hin bias current vs. supply voltage v in = supply voltage 0 5 10 15 20 25 30 0 5 10 15 20 25 30 35 40 supply voltage (v) input bias current (ua) logic "1" either input pin logic "0" 2ua max. fig. 17 fig. 18 fig.19 fig. 20 fig.21 fig.22
11 ixd611 ? 2007 ixys corporation all rights reserved low level output voltage vs. supply voltag e io = 20ma 0 20 40 60 80 100 120 140 160 180 200 0 5 10 15 20 25 30 35 supply voltage (v) low level output voltage (mv) low side high side output sink current vs. supply voltage -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0 5 10 15 20 25 30 35 40 supply voltage (v) output sink current (a) output source current vs. supply voltage 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 5 10 15 20 25 30 35 40 supply voltage (v) output source current (a) high level ouput voltag e vs. supply voltage i o = 20ma 0 50 100 150 200 250 300 0 5 10 15 20 25 30 35 supply voltage (v) high level ouput voltage (mv) low side high side output source current vs. temperature v supply = 15v 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -50 0 50 100 150 temperature (c) source current (a) output sink current vs. temeprature v supply = 15v -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 -50 0 50 100 150 temperature (c) sink current (a) fig. 23 fig. 24 fig. 25 fig. 28 fig. 27 fig. 26
12 ixd611 ixys reserves the right to change limits, test conditions, and dimensions. supply current vs. supply voltage c load = 100pf v in = v supply 50% duty cycle 0.1 1 10 100 0 5 10 15 20 25 30 35 40 supply voltage (v) supply current (ma) high side 10khz low side 10khz low side 100kh z high side 100khz 1mhz 2mhz supply current vs. supply voltage c load = 1000pf v in = v supply 50% duty cycle 0.1 1 10 100 0 5 10 15 20 25 30 35 40 supply voltage (v) supply current (ma) low side10khz 100khz 1mhz 2mhz high side10khz output resistance vs. supply voltage 0 2 4 6 8 10 12 14 0 5 10 15 20 25 30 35 40 supply voltage (v) output resistance (ohms) high state / low side low state / low side high state / high side low state / high side high to low side leakage current vs.high side v offset 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0 100 200 300 400 500 600 700 high side offset voltage (v) leakage current (ma) pulse width stability vs. temperature v cl = v ch = 15v input pw = 300ns 280 285 290 295 300 305 -50 0 50 100 150 temperature (c) pulse width out (ns) low side high side high to low side leakage current vs. temperature v offset = 600v v cl = v ch = 15v 114 116 118 120 122 124 126 128 130 132 -50 0 50 100 150 temperature (c) leakage current (ua) fig. 29 fig. 30 fig. 31 fig. 32 fig. 33 fig. 34
13 ixd611 ? 2007 ixys corporation all rights reserved normalized pw out vs. pw in (low side) v in = v supply = 10v, 20v, 30v c load = 1000pf 0 0.2 0.4 0.6 0.8 1 1.2 0 50 100 150 200 250 300 350 400 pulse width in (ns) normalized pw out normalized pw out vs. pw in (high side) v in = v supply = 10v, 20v, 30v c load = 1000pf 0 0.2 0.4 0.6 0.8 1 1.2 0 50 100 150 200 250 300 350 400 pulse width in (ns) normalized pw out 10v 20v 30v fig. 35 fig. 36
14 ixd611 ixys reserves the right to change limits, test conditions, and dimensions. ixd611p7 package ixys corporation 3540 bassett st; santa clara, ca 95054 tel: 408-982-0700; fax: 408-496-0670 e-mail: sales@ixys.net www.ixys.com ixys semiconductor gmbh edisonstrasse15 ; d-68623; lampertheim tel: +49-6206-503-0; fax: +49-6206-503627 e-mail: marcom@ixys.de IXD611S1 package ixd611p1 package ixd611s7 package 12 11 10 9 8 7 6 5 4 3 2 1 8 1.27 0.50 6.20 bsc 4.00 8.75 0.25 0.51 0.25 1.75 0 0.40 0.25 5.80 1.27 3.80 8.55 0.19 0.33 0.10 1.35 8 .050 .020 .244 bsc .157 .344 .010 .020 .010 .069 0 .016 .010 .228 .050 .150 .337 .008 .013 .004 .053 a1 a max min max min millimeters inches sym n o te: thi s d r a wi n g will m ee t a ll d im e n s i o n s r equ ir e m e nt o f j ede c m s - 0 12 ab. 14 13

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